Optimized Class-E RF Power Amplifier Design in Bulk CMOS

📖 The Scoop

The telecommunication market calls for the integration of complicated wireless applications. To build RF power amplifiers in CMOS remains challenging due to the non-ideal effects in CMOS. The aim of this thesis is to provide an optimized yet explicit design method for the Class-E amplifiers in CMOS. Taking the finite DC feed inductor into consideration, a simple but accurate numerical design method is proposed by applying polynomial interpolation. Combining with a practical design strategy for non-ideal transistors of finite conductance and parasitic capacitances, a two-staged Class-E power amplifier is implemented in 0.18mum CMOS. The simulation results show that this power amplifier can deliver at least a 23dBm power to a 50Ohm load with 73.5% PAE at 2.4GHz. The good agreement between simulation results and the predicted values validates this design method and its applications in CMOS. This method could be applied to general design cases.

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